Core architecture

The PIC architecture is distinctively minimalist. It is characterized by the following features:

* Separate code and data spaces (Harvard architecture)
* A small number of fixed length instructions
* Most instructions are single cycle execution (4 clock cycles), with single delay cycles upon branches and skips
* A single accumulator (W), the use of which (as source operand) is implied (i.e. is not encoded in the opcode)
* All RAM locations function as registers as both source and/or destination of math and other functions.[1]
* A hardware stack for storing return addresses
* A fairly small amount of addressable data space (typically 256 bytes), extended through banking
* Data space mapped CPU, port, and peripheral registers
* The program counter is also mapped into the data space and writable (this is used to implement indirect jumps).

Unlike most other CPUs, there is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers.

Data space (RAM)

PICs have a set of registers that function as general purpose RAM. Special purpose control registers for on-chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC devices have some banking mechanism to extend the addressing to additional memory. Later series of devices feature move instructions which can cover the whole addressable space, independent of the selected bank. In earlier devices (i.e., the baseline and mid-range cores), any register move had to be achieved via the accumulator.

To implement indirect addressing, a "file select register" (FSR) and "indirect register" (INDF) are used: A register number is written to the FSR, after which reads from or writes to INDF will actually be to or from the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer.

External data memory is not directly addressable except in some high pin count PIC18 devices.

Code space

All PICs feature Harvard architecture, so the code space and the data space are separate. PIC code space is generally implemented as EPROM, ROM, or flash ROM.

In general, external code memory is not directly addressable due to the lack of an external memory interface. The exceptions are PIC17 and select high pin count PIC18 devices.

Word size

The word size of PICs can be a source of confusion. All PICs handle (and address) data in 8-bit chunks, so they should be called 8-bit microcontrollers. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline and mid-range families have program memory addressable in the same wordsize as the instruction width, ie. 12 or 14 bits respectively. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differs from the instruction width of 16 bits.


In order to be clear, the program memory capacity is usually stated in number of (single word) instructions, rather than in bytes.

Stacks

PICs have a hardware call stack, which is used to save return addresses. The hardware stack is not software accessible on earlier devices, but this changed with the 18 series devices.

Hardware support for a general purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture more friendly to high level language compilers.

Instruction set

A PIC's instructions vary from about 35 instructions for the low-end PICs to over 80 instructions for the high-end PICs. The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a register, as well as for conditional execution, and program branching.

Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W; writing the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the "high end" cores.

PIC cores have skip instructions which are used for conditional execution and branching. The skip instructions are: 'skip if bit set', and, 'skip if bit not set'. Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip (with the opposite condition) followed by an unconditional branch. Skips are also of utility for conditional execution of any immediate single following instruction.

The PIC architecture has no (or very meager) hardware support for automatically saving processor state when servicing interrupts. The 18 series improved this situation by implementing shadow registers which save several important registers during an interrupt.

In general, PIC instructions fall into 5 classes:

1. Operation on W with 8-bit immediate ("literal") operand. E.g. movlw (move literal to W), andlw (AND literal with W). One instruction peculiar to the PIC is retlw, load immediate into W and return, which is used with computed branches to produce lookup tables.
2. Operation with W and indexed register. The result can be written to either the W register (e.g. addwf reg,w). or the selected register (e.g. addwf reg,f).
3. Bit operations. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible.
4. Control transfers. Other than the skip instructions previously mentioned, there are only two: goto and call.
5. A few miscellaneous zero-operand instructions, such as return from subroutine, and sleep to enter low-power mode.

Interrupt Latency

A very useful and unique property of PICs is that their interrupt latency is constant (it's also low: 3 instruction cycles). The delay is constant even though instructions can take one or two instruction cycles: a dead cycle is optionally inserted into the interrupt response sequence to make this true. External interrupts have to be synchronized with the four clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized.

The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. An example of this is a video sync pulse generator. Other microcontrollers can do this in some cases, but it's awkward. The non-interrupt code has to anticipate the interrupt and enter into a sleep state before it arrives. On PICs, there is no need for this.

The three-cycle latency is increased in practice because the PIC does not store its registers when entering the interrupt routine. Typically, 4 instructions are needed to store the W-register, the status register and switch to a specific bank before starting the actual interrupt processing.

Limitations

The PIC architectures have several limitations:

* Only a single accumulator
* A small instruction set
* Operations and registers are not orthogonal; some instructions can address RAM and/or immediate constants, while others can only use the accumulator
* Memory must be directly referenced in arithmetic and logic operations, although indirect addressing is available via 2 additional registers
* Register-bank switching is required to access the entire RAM of many devices, making position-independent code complex and inefficient
* Conditional skip instructions are used instead of conditional branch instructions used by most other architectures

The following limitations have been addressed in the PIC18, but still apply to earlier cores:

* Indexed addressing mode is very rudimentary
* Stack:
o The hardware call stack is so small that program structure must often be flattened
o The hardware call stack is not addressable, so pre-emptive task switching cannot be implemented
o Software-implemented stacks are not efficient, so it is difficult to generate reentrant code and support local variables
* Program memory is not directly addressable, and thus space-inefficient and/or time-consuming to access. (This is true of most Harvard architecture microcontrollers.)

With paged program memory, there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups). For example, on PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2KB. For computed GOTOs, where you add to PCL, the page size is 256 bytes. In both cases, the upper address bits are provided by the PCLATH register. This register must be changed every time control transfers between pages. PCLATH must also be preserved by any interrupt handler.[5]

Compiler development

These properties have made it difficult to develop compilers that target PIC microcontrollers. While several commercial compilers are available, in 2008, Microchip finally released their C compilers, C18, and C30 for their line of 18f 24f and 30/33f processors. By contrast, Atmel's AVR microcontrollers—which are competitive with PIC in terms of hardware capabilities and price, but feature a RISC instruction set—have long been supported by the GNU C Compiler.

Also, because of these properties, PIC assembly language code can be difficult to comprehend. Judicious use of simple macros can make PIC assembly language much more palatable, but at the cost of a reduction in performance. For example, the original Parallax PIC assembler "pasm" has macros which hide W and make the PIC look like a two-address machine. It has macro instructions like "mov b,a" (move the data from address a to address b) and "add b,a" (add data from address a to data in address b). It also hides the skip instructions by providing three operand branch macro instructions such as "cjne a,b,dest" (compare a with b and jump to dest if they are not equal).